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Technical Session - VLSI4 |
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| Session VLSI4: | DSP Processor Architectures (Poster) |
| Time and Place: | Friday, May 15, 1:00 pm - 3:00 pm, Ballroom 4A |
| Chair: | J. Rabaey (University of California, Berkeley, USA) |
| 1:00 pm | VLSI4.1 A RISC Architecture with Uncompromised Digital Signal Processing and Microcontroller Operation D. Martin (Siemens Microelectronics Inc., USA); R. Owen (Data/Time International, USA); [abstract] [manuscript] |
| VLSI4.2 Real Time Execution of Optimal Edge Detectors on RISC and DSP Processors L. Lacassagne, F. Lohier (LIS/Electronique-Informatique-Applications (EIA), France); P. Garda (Laboratoire des Instruments et Systemes, France); [abstract] [manuscript] |
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| VLSI4.3 Fast 2D IDCT Implementation with Multimedia Instructions for a Software MPEG2 Decoder M. Ikekawa, E. Murata, I. Kuroda (NEC Corp - C&C Media Research Labs, Japan); [abstract] [manuscript] |
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| VLSI4.4 Associative Architecture for Fast DCT Y. Shain, A. Akerib, R. Adar (Associative Computing Ltd., Israel); [abstract] [manuscript] |
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| VLSI4.5 Behavioral Synthesis Optimization Using Multiple Precision Arithmetic M. Ercegovac, D. Kirovski, G. Mustafa, M. Potkonjak (University of California, Los Angeles, USA); [abstract] [manuscript] |
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| VLSI4.6 4-Way Superscalar DSP Processor for Audio Codec Applications J. Kim, S. Yoo, S. Park, N. Jung, W. Ko, K. Lee, D. Youn (Yonsei University, Korea); [abstract] [manuscript] |
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| VLSI4.7 A Low-Power DSP Core Architecture for Low Bitrate Speech Codec H. Okuhata, M. Miki, T. Onoye, I. Shirakawa (Osaka University, Japan); [abstract] [manuscript] |
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| VLSI4.8 Number Representations for Reducing Switched Capacitance in Subband Coding J. Sacha, M. Irwin (Penn State University, USA); [abstract] [manuscript] |
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| VLSI4.9 An Architectural Study of a Digital Signal Processor for Block Codes W. Drescher, M. Mennenga, G. Fettweis (Dresden University of Technology, Germany); [abstract] [manuscript] |
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| VLSI4.10 Techniques for Intellectual Property Protection of DSP Designs I. Hong, M. Potkonjak (University of California, Los Angeles, USA); [abstract] [manuscript] |
| < VLSI3 |