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Technical Session -  VLSI3   
 
Session VLSI3:    DSP Development Tools   (Lecture)
Time and Place:    Thursday, May 14,  3:30 pm - 5:30 pm,  Room 607
Chair:    I. Verbauwhede (ATMEL, Berkeley, USA)
 
 
3:30 pm    VLSI3.1
Software Pipelining of Nested Loops for Real-Time DSP Applications
J. Wang  (Speech Recognition Software, Nortel Montreal Lab., Canada);   B. Su  (William Paterson University of New Jersey, USA);  
[abstract] [manuscript]
 
3:45 pm    VLSI3.2
Improving the Throughput of Flexible-Precision DSPs via Algorithm Transformation
M. Aggarwal, N. Shanbhag, N. Ahuja  (University of Illinois, USA);  
[abstract] [manuscript]
 
4:00 pm    VLSI3.3
Loop Scheduling Algorithms for Power Reduction
Z. Yu, F. Chen, E. Sha  (University of Notre Dame, USA);  
[abstract] [manuscript]
 
4:15 pm    VLSI3.4
Performance Evaluation of Register Allocator for the Advanced DSP of TMS320C80
J. Kim  (Seoul National University, Korea);   G. Short  (Texas Instruments, UK);  
[abstract] [manuscript]
 
4:30 pm    VLSI3.5
Low-Power Reconfigurable Signal Processing via Dynamic Algorithm Transformations (DAT)
M. Goel, N. Shanbhag  (University of Illinois, USA);  
[abstract] [manuscript]
 
4:45 pm    VLSI3.6
Pipelined Hogenauer CIC Filters Using Field-Programmable Logic and Residue Number System
A. Garcia  (University of Granada, Spain);   U. Meyer-Baese, F. Taylor  (University of Florida, USA);  
[abstract] [manuscript]
 
5:00 pm    VLSI3.7
Synthesis of Folded, Pipelined Architectures for Multi-Dimensional Multirate Systems
V. Sundararajan, K. Parhi  (University of Minnesota, USA);  
[abstract] [manuscript]
 
5:15 pm    VLSI3.8
Minimization of Data Address Computation Overhead in DSP Programs
B. Wess, M. Gotschlich  (University of Technology, Vienna, Austria);  
[abstract] [manuscript]
 
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