HomeChair: Wayne Burleson, University of Massachusetts, USA
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Martin Gumm, C3I/EPFL (Switzerland)
Friederich Mombers, C3I/EPFL (Switzerland)
Stephanie Dogimont, C3I/EPFL (Switzerland)
Daniel Mlynek, C3I/EPFL (Switzerland)
A class of motion estimation VLSI architectures is presented which has been developed for the usein studio quality MPEG2 encoders. A new, fast motion estimation algorithm is applied which exploits both, temporal and spatial redundancies in motion vector fields and delivers near full search quality on large search windows. The proposed architectures are MIMD based, scalable both on chip and system level, and provide high flexibility according to a programmable RSIC/co-processor approach. A chip tailored to TV resolution requirements is under design. The same architecture principle can be used to build HDTV capable motion estimation devices.
ic981678.pdf (From Postscript)
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S.R. Park, University of Massachusetts (U.S.A.)
Wayne Burleson, University of Massachusetts (U.S.A.)
In this paper we propose a reconfigurable approach to motion estimation. The statistics of motion vectors can be monitored on a frame by frame basis to choose appropriate hardware configurations. A novel aspect of this work is that we use power savings as a motivation for the reconfiguration. Although FPGAs are not a very power efficient technology, careful design of array architectures can allow power to be saved by avoiding unnecessary computation. This is done by adjusting the search area according to the changing characteristics of an input video signal. Unlike some proposed applications of dynamic reconfiguration, this rate can easily be supported by existing FPGA technology. A more general result is that further power saving can be achieved by utilizing free FPGA resources as local memory to avoid power-hungry off-chip communication. Practical implementation issues using Xilinx 6200 series FPGAs are also discussed.
ic982310.pdf (From Postscript) TOP
Yukihiro Naito, NEC Corporation (Japan)
Ichiro Kuroda, NEC Corporation (Japan)
This paper describes an H.263 video codec implementation based on a low power consumption general purpose DSP. Fast algorithms, such as a fast motion estimation algorithms and a low complexity noise reduction filter, are proposed to implement the video codec on a single DSP chip maintaining sufficient picture quality. By using a 50MIPS, 100mW DSP, the developed codec encodes and decodes 7.5 QCIF frames per second, which is sufficient performance for low bit-rate video compression, typically below 64kbps.
ic981313.pdf (From Postscript) TOP
Oskar Mencer, Stanford University (U.S.A.)
Martin Morf, Stanford University (U.S.A.)
Michael J Flynn, Stanford University (U.S.A.)
We explore the design space of Field Programmable Gate Arrays (FPGAs), Processors and ASICs -- Hardware-Software Tri-design -- in the framework of encryption for hand-held communication units. IDEA (International Data Encryption Algorithm) is used to show thetradeoffs for the suggested technologies. The measures for comparing different options are: Performance, Programmability and Power ($P^3$). More specifically we use the Performance to Power, or Operations to Energy ratio MOPS/Watt and Mbits/s/Watt to compare processors, FPGAs and ASICs. We compare the latest Digital Signal Processor (DSP) from Texas Instruments to Xilinx XC4000 series FPGAs. Many DSP-like applications perform very well on FPGAs. We show the benefits and limitations of FPGA technology for IDEA.
ic982332.pdf (From Postscript) TOP
Leilei Song, University of Minnesota (U.S.A.)
Keshab K. Parhi, University of Minnesota (U.S.A.)
Ichiro Kuroda, NEC Corporation (Japan)
Takao Nishitani, NEC Corporation (Japan)
Reed-Solomon (RS) codecs are used for error control coding in many applications such as digital audio, digital TV, software radio, CD players, and wireless and satellite communications. This paper considers software-based implementation of RS codecs where special instructions are assumed to be used to program finite field multiplication datapaths inside a domain-specific programmable digital-signal processor (DS-PDSP). A heterogeneous digit-serial approach is presented, where the heterogeneity corresponds to the use of different digit-sizes in the multiply-accumulate (MAC for polynomial multiplication) and degree reduction (DEGRED for polynomial modulo operation) subarrays. The salient feature of this digit-serial approach is that only the digit-cells are implemented in hardware, the finite field multiplications are performeddigit-serially in software by dynamically scheduling the internal digit-level operations in RS encoders and decoders. A hardware-software co-design approach is used to select the best digit-size parameters and minimize the energy consumption of both RS encoders and decoders. Low-energy Reed- Solomon codecs are designed in software based on various finite field datapath architectures. It is concluded that, for 2-error-correcting RS(n,k) codec implementations over finite field GF(2^8), a parallel MAC unit (of digit-size 8) and a DEGRED unit with digit-size 2 is the best datapath, with respect to least energy consumption and energy-delay products; with this datapath architecture and appropriate digit-serial scheduling strategies, more than 60% energy reduction and more than 1/3 energy-delay reduction can be achieved compared with the parallel multiplication datapath based aproach.
ic981344.pdf (From Postscript) TOP
Eric Dujardin, Philips (France)
Olivier Gay-Bellile, Philips (France)
More and more applications have software implementations in order to cope with the cohabitation of several emerging standards and the fast evolution of consumer products. We show in this paper how to implement efficiently digital communications applications into DSPs with the help of the Convolution Co-Processors, which is described in this paper, and how co-processors are useful to empower DSP performances at a small cost. ADSL application is taken as an example for broadband communications.
ic981958.pdf (From Postscript) TOP
Jamil Chaoui, Texas Instruments (France)
Sebastien de Gregorio, Texas Instruments (France)
Daravith Kho, Texas Instruments (France)
Stephane Sintes, Texas Instruments (France)
Yves Masse, Texas Instruments (France)
This paper describes the implementation of a car handsfree speech enhancement application on a TI TMS320C54x DSP. This fixed-point DSP family is especially suited for wireless applications and it is shown how, by taking full advantage of the DSP architecture and instruction set, advanced wireless speech processing applications can be efficiently implemented on these devices. The performances of the complete speech enhancement application in a car environment are presented, showing that even with a fixed-point arithmetic implementation, high performances close to a floating point implementation can be achieved.
ic981293.pdf (From Postscript) TOP
Marco Felici, University of Bologna (Italy)
Michele Borgatti, University of Bologna (Italy)
Alberto Ferrari, University of Bologna (Italy)
Roberto Guerrieri, University of Bologna (Italy)
A low-power feature extraction chip computing cepstral coefficients from linear predictive analysis on one-bit quantized speech signal is presented and its VLSI implementation is evaluated. An isolated-word small-vocabulary speech recognizer based on these features has been developed. Its recognition accuracy is within 2% below a system based on standardlinear predictive cepstral features. The power consumption of the feature extractor chip is 30uW at 0.9V.
ic981464.pdf (From Postscript) TOP