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Technical Session - SPEC-VLSI

Session SPEC-VLSI:	Multimedia DSP Processors (Lecture)
Time and Place:	Wednesday, May 13, 9:30 am - 11:00 am, Room 604
Chair:	W. Gass (Texas Instruments, USA)

9:30 am	SPEC-VLSI.1 Design Space Exploration for Future TriMedia CPUs F. Sijstermans, E. Pol, B. Riemens, K. Vissers (Philips Research, The Netherlands); S. Rathnam, G. Slavenburg (Philips Semiconductors TriMedia, Sunnyvale, California, USA); [abstract] [manuscript]
9:45 am	SPEC-VLSI.2 Software MPEG-2 Video Decoder on a 200-Mhz, Low-Power Multimedia Microprocessor K. Nadehara (NEC Corporation, Japan); L. Hanno (University of Hannover, Germany); I. Kuroda (NEC Corporation, Japan); [abstract] [manuscript]
10:00 am	SPEC-VLSI.3 Codevelopment of the TMS320C6x VelociTI Architecture and Compiler R. Simar Jr. (Texas Instruments, USA); [abstract] [manuscript]
10:15 am	SPEC-VLSI.4 TI DSP Implementation of A Medium Speed DSL (MDSL) for Multimedia Applications S. Wu, X. Lu, W. Chen (TI, USA); [abstract] [manuscript]
10:30 am	SPEC-VLSI.5 A Flexible Processor Architecture for MPEG-4 Image Compositing M. Berekovic, R. Frase, P. Pirsch (Laboratorium für Informationstechnologie, Germany); [abstract] [manuscript]
10:45 am	SPEC-VLSI.6 Multimedia Applications of Microprocessor with Embedded DRAM Y. Nunomura, T. Shimizu, K. Saitoh, K. Tsuchihashi (Mitsubishi Electric Corporation, Japan); [abstract] [manuscript]