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Abstract - DSP14 |
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DSP14.1 |
Integration of DSP Algorithms and Musical Constraints for the Separation of Partials in Polyphonic Music R. Mani, H. Nawab (Boston University, USA) We illustrate how high-level knowledge from the musical domain may be integrated with sophisticated signal processing algorithms within a system for separating possibly overlapping partial frequency components from polyphonic music. Musical knowledge utilized in our system is in the form of constraints on the time-frequency behaviors of musical signals such as the frequency locations of notes on the western musical scale and the presence or absence of vibrato in each note. For any given signal scenario, these constraints help in appropriately initializing and adjusting a set of algorithms for constant-Q processing, spectral peak picking, and multihypothesis tracking through Kalman filtering. As demonstrated by the evaluation of our system with a variety of signals containing two simultaneously played violin notes, the application of these algorithms results in the accurate separation of individual partials. |
| DSP14.2 |
An Implementation of a Parallel Ray Tracing Algorithm on Hybrid Parallel Architecture C. Kwon, H. Sung, H. Choi (Kyungpook National University, Korea) In this paper, we present a parallel ray tracing algorithm on hybrid parallel architecture with processor farm model to speed up the ray tracing. Hybrid parallel architecture, a hybrid of a tightly- and a loosely-coupled one, is used in which reconfiguration for local and virtual shared memory is made through a crossbar network with local and global bus. The proposed architecture enhances the overall performance of the parallel ray tracing by reducing the data communication time between the processors in dynamic load balancing while maintaining data coherency. The proposed algorithm is implemented on TMS320C80, an MVP (multimedia video processor), which has one master processor and four slave processors. The experimental results show that the proposed algorithm gives almost a linear speedup for parallel ray tracing of a complex image. |
| DSP14.3 |
Distributed Signal Processing L. Lee, A. Oppenheim (MIT Research Laboratory of Electronics, USA) This paper explores issues arising from designing digital signal processing algorithms for dynamically-varying computing environments such as an unreliable network of processors. We present a language for specifying signal processing algorithms which permits the execution path of the algorithm to be dynamically chosen. The language leads naturally to a graphical representation of the algorithm with interesting interpretations. Finally, we formulate and characterize the solution for the problem of dynamically and optimally choosing the execution path of algorithms to minimize a system-wide cost function such as expected congestion. |
| DSP14.4 |
A Noise-Robust Echo Canceller on V830 Multimedia RISC Processor Integrated into a Car Navigation System Y. Hiratani (NEC IC Microcomputer Systems Ltd, Japan); A. Hirano (NEC Corporation, Japan); M. Kanazawa (NEC IC Microcomputer Systems Ltd, Japan) This paper presents a noise-robust, fast-convergence echo canceller and its implementation on a multimedia RISC (Reduced Instruction Set Computer). Faster convergence is achieved by introducing an improved noise power estimator for step-size control. This echo canceller has been implemented on V830 multimedia embedded RISC and has been integrated into a car navigation system. V830 provides performance comparable to a digital signal processor (DSP) and extended flexibility while power consumption is lower than that of a DSP. Computer simulations and measurements using a V830 board show fast convergence and robustness against disturbance such as a noise and a double-talk without double-talk detection. |
| DSP14.5 |
A Framework for the Graphical Specification and Execution of Complex Signal Processing Applications A. Sicheneder, A. Bender, E. Fuchs, R. Mandl, B. Sick (University of Passau, Germany) A framework with a tool-supported high-level specification technique is very important for the development of complex signal processing applications containing software-intensive parts (e.g. hybrid systems in automated production processes) in order to provide safe and reliable systems. In this paper we present the concept of a framework, which is an object-oriented CASE-tool offering a graphical specification ability to model and validate a given application and to control its execution. A variety of people having different programming skills is able to use this visual specification technique effectively. Especially users not being interested in implementation details can specify their application on a high abstraction level by connecting reusable and reliable components (modules representing basic algorithms). As a result, complex signal graphs representing the dataflow between the modules are created. The tool supports this software specification technique by automatic type-checking for the connections between modules and by changeable module parameters. On the other hand it is easy for software engineers to integrate additional signal processing algorithms into the framework thus building suitable module libraries without considering a specific high-level application. |
| DSP14.6 |
Computationally Efficient Implementation of Hypercomplex Digital Filters H. Toyoshima (Kanagawa University, Japan) Hypercomplex digital filters have an attractive advantage of the order reduction, however, also have a drawback that multiplication requires a large amount of computations. This paper proposes a novel implementation of hypercomplex digital filters. By decomposing hypercomplex number multiplication, we show that it can be realized as two parallel complex multiplications. Using this technique, any types of hypercomplex digital filters can be implemented with less than half computations of the direct approach. |
| DSP14.7 |
A Highly-Scalable FIR Using the RADIX-4 Booth Algorithm O. Chen, W. Liu (National Chung Cheng University, Taiwan, ROC); H. Hsieh, J. Wang (Comp & Commun Res. Lab., ITR, Taiwan, ROC) A Highly-scaleable FIR architecture based on the radix-4 Booth algorithm has been designed with scaleable dynamic ranges of input data and filter coefficients. The radix-4 Booth algorithm is demonstrated to have a lower hardware complexity and a fair throughput rate than the other radix approaches. In order to achieve scaleability, the configurable-connection function between latches of input data, and filter taps has been explored. The precision of filter coefficients is adjustable by using a path-control function. Especially, the proposed architecture only employs data-path controls to realize the scaleable issue without changing the word lengths and components of input latches and filter taps. The pre-processing unit for manipulating input data and post-processing unit for computing accumulation results have been realized to support scaleable operations. Based on our architecture in a chip design, the cascaded configuration between chips is also easily accomplished for many industrial applications. |
| DSP14.8 |
Reversible Discrete Cosine Transform K. Komatsu, K. Sezaki (University of Tokyo, Japan) In this paper a reversible discrete cosine transform (RDCT) is presented. N-point reversible transform is firstly presented, then 8-point RDCT is obtained by substituting the 2 and 4-point reversible transforms for 2 and 4-point transforms which compose 8-point discrete cosine transform (DCT), respectively. Integer input signal can be losslessly recovered, although the transform coefficients are integer numbers. If floor function is ignored in RDCT, the transform is exactly the same as DCT with determinant = 1. RDCT is also normalized so that we can avoid the problem that dynamic range is nonuniform. Simulation on continuous-tone still images shows that lossless and lossy compression efficiency of RDCT are comparable to those obtained with reversible wavelet transform. |
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